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1

[IEEE 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Bangalore, India (2007.07.11-2007.07.13)] 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Advanced ¿-FET Technology for 45 nm Technology Node

Eng, Yi-Chuen, Lin, Jyi-Tsong

Année:

2007

Langue:

english

Fichier:

PDF, 1.43 MB

english, 2007

2

RF/Analog Performance of Novel Junctionless Vertical MOSFETs

Tai, Chih-Hsuan, Lin, Jyi-Tsong, Eng, Yi-Chuen

Journal:

Integrated Ferroelectrics

Année:

2011

Langue:

english

Fichier:

PDF, 1.38 MB

english, 2011

3

[IEEE 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) - Suzhou, Jiangsu, China (2009.07.6-2009.07.10)] 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits - Advanced block oxide MOSFETs for 25 nm technology node

Chih-Hung Sun,, Lin, Jyi-Tsong, Eng, Yi-Chuen, Tzu-Feng Chang,, Lin, Po-Hiesh, Hsuan-Hsu Chen,, Chih-Hao Kuo,, Hsien-Nan Chiu,

Année:

2009

Langue:

english

Fichier:

PDF, 7.26 MB

english, 2009

4

[IEEE 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) - Suzhou, Jiangsu, China (2009.07.6-2009.07.10)] 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits - A novel self-align double gate MOSFET with source/drain tie

Po-Hsieh Lin,, Jyi-Tsong Lin,, Yi-Chuen Eng,, Hsuan-Hsu Chen,, Chih-Hao Kuo,, Chih-Hung Sun,, Hsien-Nan Chiu,, Tzu-Feng Chang,, Nai-Chuan Chuang,

Année:

2009

Langue:

english

Fichier:

PDF, 10.01 MB

english, 2009

5

Importance of $\Delta V_{{\text {DIBLSS}}}/({I}_{{\text {on}}} /{I}_{{\text {off}}})$ in Evaluating the Performance of n-Channel Bulk FinFET Devices

Eng, Yi-Chuen, Hu, Luke, Chang, Tzu-Feng, Hsu, Steven, Chiou, Chun Mao, Wang, Ted, Yang, Chih-Wei, Cheng, Osbert, Wang, Chih-Yi, Tseng, C. S., Huang, Ren, Lin, Po-Hsieh, Lu, Kuan-Yu, Chang, I-Fan, Lee

Journal:

IEEE Journal of the Electron Devices Society

Année:

2018

Langue:

english

Fichier:

PDF, 1.24 MB

english, 2018

6

Monitoring of FinFET Characteristics Using ΔVDIBLSS/(Ion/Ioff) and ΔVDIBL/(Ion/Ioff)

Eng, Yi-Chuen, Hu, Luke, Chang, Tzu-Feng, Wang, Chih-Yi, Hsu, Steven, Cheng, Osbert, Lin, Chien-Ting, Lin, Yu-Shiang, Tsai, Zen-Jay, Wang, Ted, Tseng, Touber, Yang, Chih-Wei, Hsieh, Chin-Yang

Journal:

IEEE Journal of the Electron Devices Society

Année:

2019

Langue:

english

Fichier:

PDF, 751 KB

english, 2019

7

[IEEE 2010 Silicon Nanoelectronics Workshop (SNW) - Honolulu, HI, USA (2010.06.13-2010.06.14)] 2010 Silicon Nanoelectronics Workshop - Design theory and fabrication process of 90nm unipolar-CMOS

Lin, Jyi-Tsong, Chen, Hsuan-Hsu, Lu, Kuan-Yu, Sun, Chih-Hung, Eng, Yi-Chuen, Kuo, Chih-Hao, Lin, Po-Hsieh, Lai, Tung-Yen, Yang, Fu-Liang

Année:

2010

Langue:

english

Fichier:

PDF, 2.03 MB

english, 2010

8

[IEEE 2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits - singapore (2008.07.7-2008.07.11)] 2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits - A novel pseudo tri-gate vertical MOSFET with source/drain tie

Jyi-Tsong Lin,, Ying-Chieh Tsai,, Yi-Chuen Eng,, Shiang-Shi Kang,, Yi-Ming Tseng,, Hung-Jen Tseng,, Po-Hsieh Lin,

Année:

2008

Langue:

english

Fichier:

PDF, 1015 KB

english, 2008

9

A Novel Vertical MOSFET with bMPI Structure for 1T-DRAM Applications: A 2-D Numerical Study

Chen, Cheng-Hsin, Lin, Jyi-Tsong, Eng, Yi-Chuen, Lin, Po-Hsieh, Chiu, Hsien-Nan, Chang, Tzu-Feng

Journal:

Integrated Ferroelectrics

Année:

2011

Langue:

english

Fichier:

PDF, 853 KB

english, 2011

10

[IEEE 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Singapore (2006.7.3-2006.7.3)] 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Ultra-Short-Channel Characteristics of Planar MOSFETs With Block Oxide

Lin, Jyi-tsong, Eng, Yi-chuen, Huang, Kuo-dong, Lee, Tai-yi, Lin, Kao-cheng

Année:

2006

Langue:

english

Fichier:

PDF, 2.91 MB

english, 2006

11

[IEEE 2007 IEEE International Conference on Integrated Circuit Design and Technology - Austin, TX, USA (2007.05.30-2007.06.1)] 2007 IEEE International Conference on Integrated Circuit Design and Technology - Misalignment of the Block Oxide Height in Self-Aligned bSPIFET

Lin, Jyi-Tsong, Eng, Yi-Chuen

Année:

2007

Langue:

english

Fichier:

PDF, 3.02 MB

english, 2007

12

[IEEE 2007 IEEE International Conference on Integrated Circuit Design and Technology - Austin, TX, USA (2007.05.30-2007.06.1)] 2007 IEEE International Conference on Integrated Circuit Design and Technology - Self-aligned Block Oxide Process for bFDSOI Devices

Eng, Yi-Chuen, Lin, Jyi-Tsong

Année:

2007

Langue:

english

Fichier:

PDF, 3.44 MB

english, 2007

13

[IEEE 2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits - singapore (2008.07.7-2008.07.11)] 2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits - Simulation of the multi-source/drain SOI MOSFET

Po-Hsieh Lin,, Shiang-Shi Kang,, Jyi-Tsong Lin,, Yi-Chuen Eng,

Année:

2008

Langue:

english

Fichier:

PDF, 638 KB

english, 2008

14

[IEEE 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) - Suzhou, Jiangsu, China (2009.07.6-2009.07.10)] 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits - Characteristics of a Local Oxidation of silicon multi-tie body polysilicon thin-film transistor

Hsien-Nan Chiu,, Jyi-Tsong Lin,, Yi-Chuen Eng,, Po-Hiesh Lin,, Tzu-Feng Chang,, Chih-Hung Sun,, Hsuan-Hsu Chen,, Chih-Hao Kuo,

Année:

2009

Langue:

english

Fichier:

PDF, 8.74 MB

english, 2009

15

[IEEE 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2010) - Singapore, Singapore (2010.07.5-2010.07.9)] 2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits - A 3-D simulation study of a novel vertical MOSFET with source-tied (STVMOS)

Chih-Hsuan Tai,, Jyi-Tsong Lin,, Yi-Chuen Eng,, Kuan-Yu Lu,, Cheng-Hsin Chen,, Yu-Che Chang,, Yi-Hsuan Fan,

Année:

2010

Langue:

english

Fichier:

PDF, 489 KB

english, 2010

16

Electrical Characterization of 10-nm π-Shaped S/D MOSFETs

Eng, Yi-Chuen, Lin, Jyi-Tsong, Fan, Yi-Hsuan, Lin, Po-Hsieh, Kuo, Chih-Hao, Chang, Yu-Che, Lu, Kuan-Yu, Chen, Cheng-Hsien, Tai, Chih-Hsuan

Journal:

Integrated Ferroelectrics

Année:

2011

Langue:

english

Fichier:

PDF, 2.00 MB

english, 2011

17

An Influence of Temperature Variation for the DC and RF/Analog Performance in a Novel Dual-Channel Source/Drain-Tied MOSFET

Fan, Yi-Hsuan, Lin, Jyi-Tsong, Eng, Yi-Chuen

Journal:

Integrated Ferroelectrics

Année:

2011

Langue:

english

Fichier:

PDF, 1021 KB

english, 2011

18

[IEEE 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) - Suzhou, Jiangsu, China (2009.07.6-2009.07.10)] 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits - Self-aligned SOI MOSFETs with Ω-shaped conductive layer and source/drain-tie

Jyi-Tsong Lin,, Tzu-Feng Chang,, Yi-Chuen Eng,, Hsuan-Hsu Chen,, Chih-Hao Kuo,, Chih-Hung Sun,, Po-Hiesh Lin,, Hsien-Nan Chiu,

Année:

2009

Langue:

english

Fichier:

PDF, 9.30 MB

english, 2009

19

[IEEE 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) - Suzhou, Jiangsu, China (2009.07.6-2009.07.10)] 2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits - A simulation study of source/drain-tie effects on characteristics of self-aligned π-shaped source/drain ultrathin SOI FETs

Yi-Chuen Eng,, Jyi-Tsong Lin,, Tzu-Feng Chang,, Chih-Hao Kuo,, Po-Hsieh Lin,, Chih-Hung Sun,, Hsien-Nan Chiu,, Hsuan-Hsu Chen,

Année:

2009

Langue:

english

Fichier:

PDF, 21.06 MB

english, 2009

20

Influence of Block Oxide Width on a Silicon-on-Partial-Insulator Field-Effect Transistor

Jyi-Tsong Lin, Yi-Chuen Eng

Journal:

IEEE Transactions on Electron Devices

Année:

2007

Langue:

english

Fichier:

PDF, 1.03 MB

english, 2007

21

A Novel Blocking Technology for Improving the Short-Channel Effects in Polycrystalline Silicon TFT Devices

Jyi-Tsong Lin, Yi-Chuen Eng

Journal:

IEEE Transactions on Electron Devices

Année:

2007

Langue:

english

Fichier:

PDF, 1.23 MB

english, 2007

22

Short-Channel Characteristics of Self-Aligned -Shaped Source/Drain Ultrathin SOI MOSFETs

Jyi-Tsong Lin, Yi-Chuen Eng, Hau-Yuan Huang, Shiang-Shi Kang, Po-Hsieh Lin, Kung-Kai Kao, Jeng-Da Lin, Yi-Ming Tseng, Ying-Chieh Tsai, Hung-Jen Tseng

Journal:

IEEE Transactions on Electron Devices

Année:

2008

Langue:

english

Fichier:

PDF, 1.14 MB

english, 2008

23

Numerical Study of a Highly Scaled Bulk MOSFET With Block Oxide and Source/Drain-Tied Structure

Yi-Chuen Eng, Jyi-Tsong Lin, Chih-Hao Kuo, Po-Hsieh Lin, Yi-Hsuan Fan, Hsuan-Hsu Chen

Journal:

IEEE Transactions on Electron Devices

Année:

2011

Langue:

english

Fichier:

PDF, 1021 KB

english, 2011

24

[IEEE 2012 12th International Workshop on Junction Technology (IWJT) - Shanghai, China (2012.05.14-2012.05.15)] 2012 12th International Workshop on Junction Technology - Junction vs. junctionless vertical MOSFET by using partial SOI structure: A 2D simulation study

Syu, Shu-Huan, Lin, Jyi-Tsong, Eng, Yi-Chuen, Hsu, Shih-Wen, Chen, Kuan-Yu, Lu, You-Ren

Année:

2012

Langue:

english

Fichier:

PDF, 1.11 MB

english, 2012

25

[IEEE 2010 International Symposium on Next-Generation Electronics (ISNE) - Kaohsiung, Taiwan (2010.11.18-2010.11.19)] 2010 International Symposium on Next Generation Electronics - Numerical study of non-classical unipolar CMOS with different embedded oxide and gate length

Sun, Chih-Hung, Lin, Jyi-Tsong, Chen, Hsuan-Hsu, Eng, Yi-Chuen, Kuo, Chih-Hao, Chang, Tze-Feng, Chen, Chun-Yu, Lin, Po-Hsieh, Chiu, Hsien-Nan

Année:

2010

Langue:

english

Fichier:

PDF, 2.08 MB

english, 2010

26

[IEEE 2011 International Conference of Electron Devices and Solid-State Circuits (EDSSC) - Tianjin, China (2011.11.17-2011.11.18)] 2011 IEEE International Conference of Electron Devices and Solid-State Circuits - Unipolar CMOS inverter based on punch-through effect with two embedded oxide structure

Lin, Chia-Hsien, Lin, Jyi-Tsong, Chen, Hsuan-Hsu, Eng, Yi-Chuen, Wang, Shih-Wei

Année:

2011

Langue:

english

Fichier:

PDF, 735 KB

english, 2011

27

[IEEE 2006 IEEE International Conference on IC Design and Technology - Padova, Italy ()] 2006 IEEE International Conference on IC Design and Technology - A Novel FDSOI MOSFET with Block Oxide Enclosed Body

Jyi-Tsong Lin,, Yi-Chuen Eng,, Kuo-Dong Huang,, Tai-Yi Lee,, Kao-Cheng Lin,

Année:

2006

Langue:

english

Fichier:

PDF, 2.72 MB

english, 2006

28

[IEEE 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Shanghai, China (2010.11.1-2010.11.4)] 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - A novel high-performance junctionless vertical MOSFET produced on bulk-Si wafer

Tai, Chih-Hsuan, Lin, Jyi-Tsong, Eng, Yi-Chuen, Lin, Po-Hsieh

Année:

2010

Langue:

english

Fichier:

PDF, 1.07 MB

english, 2010

29

[IEEE 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Shanghai, China (2010.11.1-2010.11.4)] 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - A novel planar-type body-connected FinFET device fabricated by self-align isolation-last process

Lin, Po-Hsieh, Lin, Jyi-Tsong, Chang, Yu-Che, Eng, Yi-Chuen, Chen, Hsuan-Hsu

Année:

2010

Langue:

english

Fichier:

PDF, 819 KB

english, 2010

30

[IEEE 2010 International Symposium on Next-Generation Electronics (ISNE) - Kaohsiung, Taiwan (2010.11.18-2010.11.19)] 2010 International Symposium on Next Generation Electronics - A new STI-type FinFET device structure for high-performance applications

Lin, Jyi-Tsong, Lin, Po-Hsieh, Eng, Yi-Chuen

Année:

2010

Langue:

english

Fichier:

PDF, 1.18 MB

english, 2010

31

[IEEE 2011 12th International Conference on Ultimate Integration on Silicon (ULIS) - Cork, Ireland (2011.03.14-2011.03.16)] Ulis 2011 Ultimate Integration on Silicon - RF performance of the novel planar-type body-connected FinFET fabricated by isolation-last and self-alignment process

Lin, Po-Hsieh, Lin, Jyi-Tsong, Eng, Yi-Chuen, Chang, Yu-Che

Année:

2011

Langue:

english

Fichier:

PDF, 229 KB

english, 2011

32

[IEEE 2010 International Workshop on Junction Technology (IWJT) - Shanghai, China (2010.05.10-2010.05.11)] 2010 International Workshop on Junction Technology Extended Abstracts - A highly scalable Π-shaped source/drain quasi-SOI MOS transistor

Eng, Yi-Chuen, Lin, Jyi-Tsong, Fan, Yi-Hsuan, Chang, Yu-Che, Lu, Kuan-Yu, Chen, Cheng-Hsien, Tai, Chih-Hsuan

Année:

2010

Langue:

english

Fichier:

PDF, 624 KB

english, 2010

33

[IEEE 2012 28th International Conference on Microelectronics (MIEL 2012) - Nis, Serbia (2012.05.13-2012.05.16)] 2012 28th International Conference on Microelectronics Proceedings - Design, simulation, and fabrication of a new poly-Si based capacitor-less 1T-DRAM cell

Chen, Yun-Ru, Lin, Jyi-Tsong, Chang, Tzu-Feng, Eng, Yi-Chuen, Lin, Po-Hsieh, Chen, Cheng-Hsin

Année:

2012

Langue:

english

Fichier:

PDF, 746 KB

english, 2012

34

[IEEE 2011 International Conference of Electron Devices and Solid-State Circuits (EDSSC) - Tianjin, China (2011.11.17-2011.11.18)] 2011 IEEE International Conference of Electron Devices and Solid-State Circuits - A qualitative comparison study of analog performance of junction and junctionless poly-Si TFTs

Wang, Shih-Wei, Lin, Jyi-Tsong, Eng, Yi-Chuen, Chang, Yu-Che, Lin, Chia-Hsien, Chen, Hsuan-Hsu, Lin, Po-Hsieh, Tai, Chih-Hsuan, Pai, Ching-Yao

Année:

2011

Langue:

english

Fichier:

PDF, 576 KB

english, 2011

35

[IEEE 2010 International Symposium on Next-Generation Electronics (ISNE) - Kaohsiung, Taiwan (2010.11.18-2010.11.19)] 2010 International Symposium on Next Generation Electronics - A numerical study of RF performance for a junctionless vertical MOSFET

Tai, Chih-Hsuan, Lin, Jyi-Tsong, Eng, Yi-Chuen, Lu, Kuan-Yu, Chen, Cheng-Hsin, Chang, Yu-Che, Fan, Yi-Hsuan

Année:

2010

Langue:

english

Fichier:

PDF, 1.35 MB

english, 2010

36

[IEEE 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Xian, China (2012.10.29-2012.11.1)] 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology - A CIGS thin film solar cell with dual absorber layers

Wang, Jian-Yuan, Lin, Jyi-Tsong, Kuo, Yu-Sheng, Pai, Ching-yao, Eng, Yi-Chuen

Année:

2012

Langue:

english

Fichier:

PDF, 370 KB

english, 2012

37

[IEEE 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Shanghai, China (2010.11.1-2010.11.4)] 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Numerical study of performance comparison between junction and junctionless thin-film transistors

Pai, Ching-Yao, Lin, Jyi-Tsong, Wang, Shih-Wei, Lin, Chia-Hsien, Kuo, Yu-Sheng, Eng, Yi-Chuen, Lin, Po-Hsieh, Fan, Yi-Hsuan, Tai, Chih-Hsuan, Chen, Hsuan-Hsu, Chen, Cheng-Hsin, Lu, Kuan-Yu

Année:

2010

Langue:

english

Fichier:

PDF, 922 KB

english, 2010

38

[IEEE 2012 12th International Workshop on Junction Technology (IWJT) - Shanghai (2012.05.14-2012.05.15)] 2012 12th International Workshop on Junction Technology - Simulation study of junctionless vertical MOSFETs for analog applications

Shih-Wen Hsu,, Jyi-Tsong Lin,, Yi-Chuen Eng,, Shu-Huan Syu,, Kuan-Yu Chen,, You-Ren Lu,

Année:

2012

Langue:

english

Fichier:

PDF, 1.11 MB

english, 2012

39

[IEEE 2008 International Workshop on Junction Technology (IWJT) - Shanghai, China (2008.05.15-2008.05.16)] Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08) - An advanced non-classical self-aligned quasi-SOI MOSFET with Π-shaped semiconductor conductive layer to ease ultra-shallow junction requirement

Jyi-Tsong Lin,, Yi-Chuen Eng,, Ying-Chieh Tsai,, Hung-Jen Tseng,, Yi-Ming Tseng,, Po-Hsieh Lin,, Shiang-Shi Kang,, Jeng-Da Lin,, Hau-Yuan Huang,, Kung-Kai Kao,

Année:

2008

Langue:

english

Fichier:

PDF, 629 KB

english, 2008

40

[IEEE Tutorial (ICICDT) - Grenoble, France (2008.06.2-2008.06.4)] 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial - An SOI-based self-aligned quasi-SOI MOSFET with π-shaped semiconductor conductive layer

Yi-Chuen Eng,, Jyi-Tsong Lin,, Shiang-Shi Kang,

Année:

2008

Langue:

english

Fichier:

PDF, 652 KB

english, 2008

41

[IEEE 2010 International Symposium on Next-Generation Electronics (ISNE) - Kaohsiung, Taiwan (2010.11.18-2010.11.19)] 2010 International Symposium on Next Generation Electronics - Characterization for novel non-traditional CMOS inverter composed of a junctionless NMOSFET and a gated N+-N−-P transistor

Lu, Kuan-Yu, Lin, Jyi-Tsong, Chen, Hsuan-Hsu, Eng, Yi-Chuen, Tai, Chih-Hsuan, Chen, Cheng-Hsin, Chang, Yu-Che, Fan, Yi-Hsuan

Année:

2010

Langue:

english

Fichier:

PDF, 996 KB

english, 2010

42

[IEEE 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Shanghai, China (2010.11.1-2010.11.4)] 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - A novel CMOS inverter composed of a junctionless NMOSFET and a gated N−-N-N+ transistor for ULSI applications

Lu, Kuan-Yu, Lin, Jyi-Tsong, Chen, Hsuan-Hsu, Eng, Yi-Chuen

Année:

2010

Langue:

english

Fichier:

PDF, 678 KB

english, 2010

43

[IEEE 2010 International Workshop on Junction Technology (IWJT) - Shanghai, China (2010.05.10-2010.05.11)] 2010 International Workshop on Junction Technology Extended Abstracts - Characterization of a body-tied vertical MOSFET

Lu, Kuan-Yu, Lin, Jyi-Tsong, Eng, Yi-Chuen, Tai, Chih-Hsuan, Chen, Cheng-Hsin, Chang, Yu-Che, Fan, Yi-Hsuan

Année:

2010

Langue:

english

Fichier:

PDF, 679 KB

english, 2010

44

[IEEE 2009 10th International Conference on Ultimate Integration on Silicon (ULIS - Aachen, Germany (2009.03.18-2009.03.20)] 2009 10th International Conference on Ultimate Integration of Silicon - Study of new novel FinFET device with its bodies been connected

Jyi-Tsong Lin,, Po-Hsieh Lin,, Yi-Chuen Eng,

Année:

2009

Langue:

english

Fichier:

PDF, 946 KB

english, 2009

45

[IEEE 2006 IEEE International Conference on IC Design and Technology - Padova, Italy ()] 2006 IEEE International Conference on IC Design and Technology - A Impact of Block Oxide on 50 nm Gate Length Planar MOSFETs

Jyi-Tsong Lin,, Yi-Chuen Eng,, Tai-Yi Lee,, Kao-Cheng Lin,, Kuo-Dong Huang,

Année:

2006

Langue:

english

Fichier:

PDF, 3.13 MB

english, 2006

46

[IEEE 2008 26th International Conference on Microelectronics (MIEL 2008) - Nis, Serbia and Montenegro (2008.05.11-2008.05.14)] 2008 26th International Conference on Microelectronics - A novel vertical sidewall MOSFET using smart source/body contact without floating-body effect

Tai-Yi Lee,, Jyi-Tsong Lin,, Po-Hsieh Lin,, Yi-Chuen Eng,, Kao-Cheng Lin,

Année:

2008

Langue:

english

Fichier:

PDF, 1.88 MB

english, 2008

47

[IEEE 2010 International Symposium on Next-Generation Electronics (ISNE) - Kaohsiung, Taiwan (2010.11.18-2010.11.19)] 2010 International Symposium on Next Generation Electronics - A novel vertical MOSFET with bMPI structure for 1T-DRAM application

Chen, Cheng-Hsin, Lin, Jyi-, Eng, Yi-Chuen, Lin, Po-Hsieh, Chiu, Hsien-Nan, Chang, Tzu-Feng, Tai, Chih-Hsuan, Lu, Kuan-Yu, Fan, Yi-Hsuan, Chang, Yu-Che, Chen, Hsuan-Hsu

Année:

2010

Langue:

english

Fichier:

PDF, 922 KB

english, 2010

48

[IEEE 2012 12th International Workshop on Junction Technology (IWJT) - Shanghai (2012.05.14-2012.05.15)] 2012 12th International Workshop on Junction Technology - The effects of block oxide length (Lbo) and height (Hbo) in a bMOS

Kuan Kuan-Yu Chen,, Yu Chen,, Jyi-Tsong Lin,, Yi-Chuen Eng,, Shih-Wen Hsu,, Shu-Huan Syu,, You-Ren Lu,

Année:

2012

Langue:

english

Fichier:

PDF, 1.01 MB

english, 2012

49

[IEEE 2010 International Symposium on Next-Generation Electronics (ISNE) - Kaohsiung, Taiwan (2010.11.18-2010.11.19)] 2010 International Symposium on Next Generation Electronics - A simple process of thin-film transistor using the trench-oxide layer for improving 1T-DRAM performance

Chiu, Hsien-Nan, Lin, Jyi-Tsong, Eng, Yi-Chuen, Chang, Tzu-Feng, Chen, Cheng-Hsin

Année:

2010

Langue:

english

Fichier:

PDF, 1.05 MB

english, 2010

50

[IEEE 2007 IEEE Conference on Electron Devices and Solid-State Circuits - Tainan, Taiwan (2007.12.20-2007.12.22)] 2007 IEEE Conference on Electron Devices and Solid-State Circuits - Impact of Source/Drain Tie on a 30 nm Bottom Gate MOSFETs

Lin, Jyi-Tsong, Lin, Jeng-Da, Shiang-Shi, Kang, Huang, Hau-Yuan, Kao, Kung-Kai, Eng, Yi-Chuen

Année:

2007

Langue:

english

Fichier:

PDF, 2.25 MB

english, 2007